Implementation of Energy-Efficient Input Buffer for NoC Router

Abstract

Network-on-Chip (NoC) is an efficient solution for interconnection between processor cores in Chip Multi-Processor (CMP), which will consume extra energy. This paper is focusing on the energy-efficient design of input buffers, one of the most critical components in NoC. The energy efficient input buffer is proposed for NoC routers which reduce energy consumption more significantly as compared to conventional input buffer and also give reduction in delay. We use a 65nm CMOS process in our simulation.