Energy Conversion in 64-Bit ALU Design on FPGA Using Mechanics of Capacitance

Authors

  • Sweety A Maharaja Surajmal Institute, Delhi, India Author
  • Tanesh Kumar South Asian University, New Delhi, India Author
  • B Pandey South Asian University, New Delhi, India Author
  • S.M M Islam South Asian University, New Delhi, India Author
  • Teerath Das South Asian University, New Delhi, India Author

Keywords:

Arithmetic Logic Unit (ALU), Capacitance Mechanics, Energy Conversion, FPGA, Power Mechanics

Abstract

In this paper an energy conversion in 64-bit Arithmetic Logic Unit (ALU) design is analyzed using an approach termed as Capacitance Mechanics. It is observed that when the Arithmetic Logic Unit is operated at frequencies of 1GHz, 10GHz, 100GHz and 1THz, total power is reduced to 52.70% 65.28% 67.60% and 67.85% respectively, when we are scaling down the capacitance from 50pF to 0pF. This ALU design is implemented on XC6VLX75T device Virtex-6 FPGA with -2 speed grade and FF484 package.

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Published

2014-04-30

Issue

Special Issue-3 (Apr 2014)

Section

Articles

How to Cite

Energy Conversion in 64-Bit ALU Design on FPGA Using Mechanics of Capacitance. (2014). International Journal of Current Engineering and Technology, 1(3.Special Issue), 196-199. https://ijcet.evegenis.org/index.php/ijcet/article/view/3900