Design and Simulation of Floating Point Pipelined ALU Using HDL

Abstract

Short for Arithmetic Logic Unit, ALU is one of the important components within a computer processor. It performs arithmetic functions like addition, subtraction, multiplication, division etc along with logical functions. Pipelining allows execution of multiple instructions simultaneously. Pipelined ALU gives better performance which will evaluated in terms of number of clock cycles required in performing each arithmetic operation. Floating point representation is based on IEEE standard 754. In this paper a pipelined ALU is proposed simulating five arithmetic operations namely addition, subtraction, multiplication, division and square root in the HDL environment. Simulation Results is also obtained in IP Core Generator supported by Xilinx. Synthesis is carried out on the Xilinx 13.2 platform and ISim is used for the simulation process.