Design and Implementation of MPLS for Ethernet Packets on FPGA

Authors

  • Mirza Raheber Raza Sri Siddhartha Institute of Technology, Tumkur. Author
  • Praveen Kumar Y G Sri Siddhartha Institute of Technology, Tumkur. Author
  • M. Z. Kurian Sri Siddhartha Institute of Technology, Tumkur. Author
  • K.V. Narayanswamy Dept of EEE, M.S.Ramaiah School of Advanced Studies, Bangalore. Author

Keywords:

MPLS, Ethernet, FPGA.

Abstract

This paper presents hardware architecture of Multi-Protocol Label Switching (MPLS). MPLS is a protocol used primarily to prioritize internet traffic and improve bandwidth utilization. MPLS solutions are meant to be used with Layer 2 or Layer 3 protocols. Ethernet although initially conceived as a Local Area Network technology has been steadily making roads into access and core networks. This paper presents hardware architecture to implement MPLS for Ethernet on FPGA.

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Published

2013-08-31

Issue

Vol.3, No.3 (Jul/Aug 2013)

Section

Articles

How to Cite

Design and Implementation of MPLS for Ethernet Packets on FPGA. (2013). International Journal of Current Engineering and Technology, 3(3), 825-828. https://ijcet.evegenis.org/index.php/ijcet/article/view/382