Performance Analysis of Router for Network on Chip

Authors

  • Farhina T. Ansari Dept. of Electronics Engg, G. H. Raisoni College of Engineering, India Author
  • Bharati B. Sayankar Dept. of Electronics Engg, G. H. Raisoni College of Engineering, India Author
  • Pankaj AgrawalbDept. of Electronics and Communication Engg, Shri Ramdeobaba College of Engg & Management, India Dept. of Electronics and Communication Engg, Shri Ramdeobaba College of Engg & Management, India Author

Keywords:

System on Chip, Network on Chip, Routers, Switching Techniques, Arbitration.

Abstract

Major drawback of bus based communication system is that the loading effect becomes more if the complexity of the system is increased which drops the speed further. Ad-hoc routing of wires results in backend complications, lower performance and higher power consumptions. Network on Chip (NoC) has been adopted as a new promising solution for its extensibility and power efficiency. The fundamental unit of Network on Chip is the router. In this paper, we proposed a router module with wormhole switching concept. The router module is described at RTL level using VHDL and simulated in Xilinx ISE 13.1 simulator.

References

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Published

2013-06-30

Issue

Vol.3, No.2 (Apr/Jun 2013)

Section

Articles

How to Cite

Performance Analysis of Router for Network on Chip. (2013). International Journal of Current Engineering and Technology, 3(2), 685-687. https://ijcet.evegenis.org/index.php/ijcet/article/view/323