Reconfigurable Hardware Implementation of Fused Add-Multiply Operator

Abstract

Arithmetic operations are now a days used in digital signal processing applications. Here we will focused on implementation of fused add multiply operator. For getting recoding of sum of two numbers we will implement a technique called sum of two numbers in its modified booth. We introduce three different types of recoding technique. For using actual recoding technique we will compare with Fused add multiply designs. Here the technique which will be used that reduced some factors like delay, complexity of hardware and power consume of the Fused add multiply unit.