FPGA Implementation of FIR Filter Design with Optimization of Adder Tree & Constant Multiplication

Abstract

Finite Impulse Response filter is mostly used in the digital signaling processing (DSP) applications. In FIR most important parameters are complexity, cost, and power consumption. While the research focus of resolve the thus parameter to be reduced. To use the Multiple Constant Multiplication (MCM) for optimize the adder tree in the filter. In this paper we have identified the resource minimization problem in the scheduling of adder-tree operations in MCM blocks by using Mixed Integer Programming (MIP).Result shows that up to 11.09% reduction of area and 7.66% reduction of power can be achieved on the top of already optimized adder/subtractor network of the MCM block.