Design and Implementation of Huffman Decoder for Text data Compression

Authors

  • Swapna R Department of ECE, College of Engineering Munnar, Kerala, India Author
  • Ramesh P. Department of ECE, College of Engineering Munnar, Kerala, India Author

Keywords:

Binary tree, Data compression, Decoding algorithm Huffman decoder, Verilog, FPGA.

Abstract

Digital compression of data is important due to the bandwidth limitations inherent in the transmission medium. Data compression is also called as source coding. It is the process of encoding information using fewer bits than an uncoded representation. Compression is a technology for reducing the quantity of data used to represent any content without excessively reducing the quality of the picture. It also reduces the number of bits required to store and/or transmit digital media. Compression is a technique that makes storing easier for large amount of data. There are various techniques available for compression, this paper presents Huffman decoder based on new binary tree method for improving usage of memory and Bandwidth for Text data Compression. The work mainly deals with the implementation of Huffman decoder on a Xilinx 14.7 version, using Verilog Hardware Description Language.

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Published

2015-06-30

Issue

Section

Articles

How to Cite

Design and Implementation of Huffman Decoder for Text data Compression. (2015). International Journal of Current Engineering and Technology, 5(3), 2032-2035. https://ijcet.evegenis.org/index.php/ijcet/article/view/2318