Design and Implementation of Reed Solomon (16, 8) Decoder

Abstract

Channel coding can use either Automatic Repeat request or Forward Error Correction technique depending on the properties of the system or on the application in which the error correcting is to be introduced. It is an important operation for the digital communication system transmitting digital information over a noisy channel. Error control coding techniques are based on the addition of redundancy to the information message according to a prescribed rule thereby providing data a higher bit rate. The combined goal of the channel encoder and the decoder is to minimize the channel noise. RS codes are non-binary cyclic error correcting block codes. Here redundant symbols are generated in the encoder using a generator polynomial and added to the very end of the message symbols. Then RS Decoder determines the locations and magnitudes of errors in the received polynomial. Galois field arithmetic is used for encoding and decoding of Reed – Solomon codes. Verilog implementation creates a flexible, fast method and high degree of parallelism for implementing the Reed – Solomon codes. The design is carried out by writing Verilog modules for different encoder and decoder components. The results constitute simulation of Verilog codes of different modules of the Reed – Solomon Codes.