Wallace Tree Multiplier using Compressor

Abstract

Multiplier is an important block in most of digital and high performance systems So the performance of such system can be improved by implementing high speed multiplier. Varieties of multipliers are available, in that a fast multiplier based on booth encoded Wallace tree is discussed in this research. The conventional Wallace tree multiplier is based on carry save adder. Here the speed of the multiplier is improved by introducing compressors instead of the carry save adder. 3-2 compressor, 4-2 compressor, 5-2 compressors and 7-2 compressors are used with Wallace tree multiplier. Higher order compressors have better performance compared with 3-2 compressor. So the speed of the multiplier can be improved by introducing the higher order compressors. The coding is done on Verilog HDL and synthesis is done by using Xilinx ISE 14.7. Further analysis is done by using Cadence Encounter tool. Various design parameters like delay, area, power of Wallace booth multiplier with various compressors and different radix are analyzed.