Multiple Word Length Optimization based algorithm and architecture for low power QPSK base band receiver

Abstract

The necessity of low power VLSI circuits in wireless communication applications is increasing with high pace. In wireless communication IC design, research on power optimization methods by reducing the word-lengths in digital implementation of algorithms is gaining importance. The optimum word length selection for each signal in an algorithm is crucial for Word length optimization (WLO). In this paper, we present an algorithm for optimal Multiple Word-Length (MWL) computation at every signal stage in base band receiver using system level parameters. The word length, which is sufficient to carry signals with minimum acceptable Signal to Quantization Noise Ratio (SQNR) is computed at every stage and applied to a scalable Register Transfer Level (RTL) design. The Power optimized RTL model is simulated and the resulted SER values are compared with theoretical values. At each optimization, level area and power analysis are also carried out. Xilinx tools are used for timing and power analysis. The optimized architecture demonstrates a power saving of 40% for Es/No = 8 dB, in comparison to the 16-bit Uniform Word Length (UWL) based design for Zynq 7Z020 device based receiver. The bit accurate simulation results show less than 2 dB variation with the theoretical SER curves for different input SNR values at input. The results demonstrate a promising direction of VLSI optimization based on SNR requirement and MWL technique in Wireless Communication applications.
Categories and Subject Descriptors: Low power VLSI, Digital Signal Processing.
General Terms: Low power VLSI Design, Word Length Optimization (WLO), Signal to Quantization Noise Ratio (SQNR)