“FPGA Implementation of FIR Filter Design with Optimization of Adder Tree & Constant Multiplication”, Int. J. Curr. Eng. Technol., vol. 5, no. 3, pp. 2128–2137, Jun. 2015, Accessed: Apr. 06, 2026. [Online]. Available: https://ijcet.evegenis.org/index.php/ijcet/article/view/2364