FPGA Implementation of FIR Filter Design with Optimization of Adder Tree & Constant Multiplication. International Journal of Current Engineering and Technology, [S. l.], v. 5, n. 3, p. 2128–2137, 2015. Disponível em: https://ijcet.evegenis.org/index.php/ijcet/article/view/2364. Acesso em: 6 apr. 2026.