Performance Evaluation of 8-Bit Vedic Multiplier with Brent Kung Adder

Abstract

As multiplication influences the overall performance of system design, so the demand of high speed multipliers is increasing day by day. In this paper, 8X8 Vedic multiplier using Brent Kung adder is designed. Vedic Mathematics improves the speed of multiplier. It is the ancient Indian system of mathematics which is based on 16 sutras. Urdhva Tiryagbhyam sutra has been used for multiplication purpose. When design of Vedic multiplier using MUX based adder is compared with proposed multiplier, the proposed multiplier reduces delay .It is the advantage of proposed multiplier since it increases the speed. Verilog Hardware Description Language is used for coding. The proposed multipliers are synthesized using XILINX ISE 14.7. For simulation purpose ISim simulator has been used.