High Speed Reconfigurable Architecture for Phelix

Abstract

Phelix is 32 bit symmetric stream cipher. It provides encryption as well as authentication with inbuilt MAC function. It is compatible with both hardware and software. It is double faster than best one AES encryption algorithm. Throughput of existing Phelix cipher was increased by replacing the existing 232 modulo ripple carry adder with modulo Carry Look ahead Adder (CLA). Proposed adder reduces critical path delay in modulo addition operation. Input given to Phelix is a 128 bit nonce (N), 256 bit key (K) and plaintext (P). It also produces a MAC tag for authentication. Key stream generated from Phelix is XORed with plaintext to produce cipher text. Proposed architecture was coded by using VHDL language and device used was Xilinx Spartan3E, XC3S500E with package FG320.