Pipelined structure of Modified Booth’s Multiplier

Abstract

This paper describes a novel pipelined architecture of high speed modified Booth’s multiplier. The proposed multiplier structure is based on modified Booth’s algorithm and parallel processing techniques which are most widely used to accelerate the multiplication speed. The Carry and Save Adders are used for the intermediate stages and ripple carry adder for the last stage. Signed and unsigned multiplications can be done using the same hardware. Verilog HDL has been used to simulate the design and Xilinx has been used for delay measurement.