Enhanced Delay-based Dual-rail Precharge Logic against Leakage Power Analysis Attack

Abstract

Information security can be achieved through cryptographic algorithms. Even though they are at most secured. The physical implementation of the encryption algorithm leaks side-channel information that can be used by an attacker to reveal the secret key. Crypto circuits can be attacked by third parties using differential power analysis, which uses power consumption dependence on data being processed to reveal critical information. To protect security devices against this issue, differential logic styles with constant power dissipation are widely used. This project extends the analysis of the effectiveness of Leakage Power Analysis (LPA) attacks to cryptographic VLSI circuits. This project circuit level countermeasure against DPA is adopted. The proposed solutions leak less information than typical DDPL gates, increasing security and with negligible performance degradation.