Sub word Partitioning and Signal Value based Clock gating Scheme for Low Power VLSI Applications. International Journal of Current Engineering and Technology, [S. l.], v. 5, n. 3, p. 1762–1770, 2015. Disponível em: https://ijcet.evegenis.org/index.php/ijcet/article/view/2219. Acesso em: 4 apr. 2026.